This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2001-216668, filed on Jul. 17, 2001 and P2002-49076, filed on Feb. 26, 2002; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a high withstand voltage semiconductor device.
2. Description of the Related Art
PN junction diodes, Schottky barrier diodes, MOSFETs and IGBTs are among high withstand voltage devices that can operate as switching or amplifying elements for power applications. Known withstand voltage structures of such devices include field plate structures, guard ring structures and RESURF (reduced surface field) structures. These structures will be briefly described below in terms of the structure of a Schottky barrier diode.
A high withstand voltage semiconductor device is typically formed by arranging a Schottky junction electrode at the center of the front surface of an nxe2x88x92 first conductivity type substrate with a low impurity concentration and forming an opposing electrode, utilizing the rear surface of the substrate as n+ layer. Then, a withstand voltage structure is arranged to surround the Schottky junction electrode so as to eliminate possible appearance of an intensified electric field from the outer periphery of the Schottky junction electrode. When a reverse bias voltage is applied between the electrodes, the depletion layer expands from an area immediately surrounding the junction electrode on the substrate surface toward the inside of the substrate, although it can hardly expand toward the outer periphery of the substrate surface due to the influence of the fixed charge in the oxide film and other factors so that the electric field is locally intensified to give rise to a breakdown of the junction. Therefore, a high withstand voltage device is realized by using a withstanding structure that is adapted to expand the depletion layer toward the terminal outer periphery of the substrate in a well balanced manner.
FIG. 20 of the accompanying drawings is a schematic cross sectional view of a field plate structure. It shows a Schottky barrier diode comprising a Schottky junction electrode 102 and an opposing electrode 103 arranged respectively on the front surface and the rear surface of an nxe2x88x92 type substrate 101. An edge termination layer 104 of a p+ well is arranged along the outer edge of the Schottky junction electrode 102, while an n+ channel stopper layer 105 is arranged along the outermost peripheral edge of the substrate. The region of the substrate between these layers is a terminating region. The surface of the substrate is coated with an oxide film 106 between the Schottky junction electrode 102 and the channel stopper layer 105. A color-shaped metal field plate 107 is arranged on the oxide film 106 over an area extending from the Schottky junction electrode 102 to the outer periphery.
As a reverse bias voltage is applied to the opposing electrode 103 and the channel stopper layer 105 relative to the Schottky junction electrode 102 in a non-conducting state, the depletion layer expands from the Schottky junction electrode 102. Since the field plate 107 and the Schottky junction electrode 102 are at a same potential level, the electric charge in the oxide film 106 is neutralized and consequently the depletion layer can easily expand on the substrate surface to reduce the potential gradient and make it possible to secure a high withstand voltage. This structure is characterized in the fact that a high withstand voltage region can be established in a small area, although the oxide film 106 can be broken down when a strong electric field is applied. Therefore, the oxide film 106 is accompanied by a problem of reliability.
FIG. 21 illustrates a guard ring structure. A number of p+ wells are arranged to surround a Schottky junction electrode 102 and form a guard ring 108. When a reverse bias voltage is applied in a non-conducting state, the depletion layer starts expanding from the edge termination layer 104 of the electrode 102 and gets to the first p+ guard ring 108. As the application of the voltage is kept on, the depletion layer expands further from the guard ring 108 and eventually gets to the outermost guard ring 108. This structure provides an advantage that a stable withstand voltage can be realized with ease. However, since the gaps separating adjacent guard rings 108 cannot be reduced remarkably, it is difficult to establish a high withstand voltage region in a small area. Additionally, the withstand voltage can vary significantly depending on the gaps separating adjacent guard rings.
FIG. 22 illustrates a withstand voltage structure formed on the principle of RESURF. This structure is realized by forming a RESURF layer 109 of a low impurity concentration pxe2x88x92 well on the outer periphery of the edge termination layer 104 that is arranged along the edge of the Schottky junction electrode 102. The depletion layer starts expanding from the pn junction between the RESURF layer 109 and the n substrate 101 when a reverse bias voltage is applied. However, since the impurity concentration of the RESURF layer 109 is low, the depletion layer also expands into and completely depletes the layer 109. As a result, the RESURF layer 109 also bears the voltage and realizes a high withstand voltage. Like the field plate structure, this structure is also adapted to reduce the area requirement.
A high withstand voltage semiconductor device having a RESURF structure can achieve a withstand voltage close to the ideal one calculated from the thickness and the impurity concentration of the substrate by optimizing the impurity concentration, the width, the depth and other parameters of the RESURF layer 109
However, if the RESURF 109 shows a high impurity concentration, the electric field can be converged to the end of the RESURF layer 109 to reduced the withstand voltage because the RESURF layer 109 is not completely depleted. If, on the other hand, the impurity concentration of the RESURF layer 109 is too low, the layer becomes depleted to reduce the effect of alleviating the electric field at the end of the edge termination layer 105 and lower the withstand voltage even when the applied voltage is still low.
Thus, the peak withstand voltage can be optimized by optimizing the impurity concentration of the RESURF layer 109. The peak withstand voltage also depends on the width of the RESURF layer 109 and the withstand voltage increases as a function of the length of the RESURF layer 109 to make it close to the ideal one.
On the other hand, the maximum withstand voltage of the RESURF structure is very critical relative to the impurity concentration of the low impurity concentration layer that constitutes the RESURF layer and remarkably falls when the impurity concentration is not optimized. Particularly, in the case of a high withstand voltage semiconductor device comprising an SiC substrate, the impurity concentration of the RESURF layer can vary widely because of the difficulty of controlling the impurity activation ratio. This means that the process of manufacturing high withstand voltage semiconductor devices is subject to variances to consequently disperse the withstand voltage characteristics of products. Then, it is difficult to provide high quality semiconductor devices on a reliable basis.
In view of the above identified problems, it is therefore the object of the present invention to provide a high withstand voltage semiconductor device having a RESURF structure that can maintain its high withstand voltage regardless of variances in the impurity concentration of the RESURF layer.
A structure formed on the condition of completing depleting the RESURF layer as in the case of a composite structure of RESURF structure and guard ring structure as proposed in Japanese Patent Application No. 8-306937 cannot show a high withstand voltage in a concentration range above the optimal concentration of the RESURF layer. The present invention is aimed at maintaining a high withstand voltage in a concentration range above the optimal concentration of the RESURF layer.
Additionally, a composite structure of RESURF structure and guard ring structure as proposed in Japanese Patent Application No. 8-306937 cannot show a high withstand voltage in a concentration range below the optimal concentration of the RESURF layer. The present invention is aimed at maintaining a high withstand voltage in a concentration range below the optimal concentration of the RESURF layer.
In an aspect of the invention, there is provided a high withstand voltage semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first electrode formed on part of the front surface of said semiconductor layer;
a second electrode formed on the rear surface of said semiconductor layer;
a first low impurity concentration semiconductor region of a second conductivity type formed on the front surface of said semiconductor layer;
a first high impurity concentration semiconductor region of the second conductivity type formed in the inside of said first low impurity concentration semiconductor region and arranged so as to overlap an end of said first electrode;
a second high impurity concentration semiconductor region of the second conductivity type formed inside said first low impurity concentration semiconductor region and arranged so as to surround said first high impurity concentration semiconductor region with a gap separating therebetween; and
a second low impurity concentration semiconductor region of the second conductivity type formed on the surface of said semiconductor layer and arranged so as to surround said first low impurity concentration semiconductor region with a gap separating therebetween.
Preferably, said first low impurity concentration semiconductor region has a width not smaller than the largest value of the depletion layer that expands when a high voltage is applied to and breaks down said first conductivity type semiconductor layer (as expressed by Emax*eps/(q*Nd), when the largest breakdown electric field is Emax (V/m), the dielectric constant of the semiconductor is eps (F/m), the unit electric charge is q (C) and the impurity concentration of the semiconductor layer is Nd (1/m3).
In another aspect of the invention, there is provided a high withstand voltage semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first electrode formed on part of the front surface of said semiconductor layer;
a second electrode formed on the rear surface of said semiconductor layer;
a a RESURF layer of a low impurity concentration semiconductor region of the second conductivity type formed on the front surface of said semiconductor layer;
an edge termination layer of a high impurity concentration semiconductor region of the second conductivity type formed in the inside of said RESURF layer and arranged so as to overlap an end of said first electrode;
an inner ring of a high impurity concentration semiconductor region of the second conductivity type formed in the inside of said RESURF layer and arranged so as to surround said edge termination layer with a gap separating therebetween; and
an outer ring of a low impurity concentration semiconductor region of the second conductivity type formed on the surface of said semiconductor layer and arranged so as to surround said RESURF layer with a gap separating therebetween.
Preferably, the RESURF layer has a width not smaller than the largest value of the depletion layer that expands when a high voltage is applied to and breaks down said first conductivity type semiconductor layer (as expressed by Emax*eps/(q*Nd), when the largest breakdown electric field is Emax (V/m), the dielectric constant of the semiconductor is eps (F/m), the unit electric charge is q (C) and the impurity concentration of the semiconductor layer is Nd (1/m3)).
Then, if the dose of the first low impurity concentration semiconductor region, or the RESURF layer, varies from the optimal dose (as expressed by=Emax*eps/q), when the largest breakdown electric field is Emax (V/m), the dielectric constant of the semiconductor is eps (F/m) and the unit electric charge is q (C)), the withstand voltage of the device is prevented from falling due to the effect of the inner and outer rings.
In still another aspect of the invention, there is provided a high withstand voltage semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first electrode formed on part of the front surface of said semiconductor layer;
a second electrode formed on the rear surface of said semiconductor layer;
a first low impurity concentration semiconductor region of a second conductivity type formed on the front surface of said semiconductor layer;
a dose of said first low impurity concentration semiconductor region being greater than the optimal dose, the width of said first low impurity concentration semiconductor region being greater than the largest value of that of the depletion layer; and
a second low impurity concentration semiconductor region of the second conductivity type formed on the surface of the front surface of said semiconductor layer and arranged so as to surround said first low impurity concentration semiconductor region with a gap therebetween;
The above defined simple structure comprising an outer ring formed around the first low impurity concentration semiconductor region and having an impurity concentration substantially same as the latter is effective for preventing the withstand voltage from falling when the impurity concentration of the first low impurity concentration semiconductor region is higher than the optimal level due to the functional feature of the outer ring.
While the surface area of the device may be slightly greater than those of comparable known devices because of the arrangement of one or more than one outer rings around the first low impurity concentration semiconductor region, such an increased area does not give rise to any problem because the number of outer rings is minimal.
In still another aspect of the invention, there is provided a high withstand voltage semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first electrode formed on part of the front surface of said semiconductor layer;
a second electrode formed on the rear surface of said semiconductor layer;
a first low impurity concentration semiconductor region of a second conductivity type formed on the front surface of said semiconductor layer;
the dose of said first low impurity concentration semiconductor region being smaller than the optimal dose, the width of said first low impurity concentration semiconductor region being greater than the largest value of that of the depletion layer; and
a first high impurity concentration semiconductor region of the second conductivity type formed in the inside of said first low impurity concentration semiconductor region and arranged so as to overlap an end of said first electrode; and
a second high impurity concentration semiconductor region of the second conductivity type formed in the inside of said first low impurity concentration semiconductor region and arranged so as to surround said first high impurity concentration semiconductor region with a gap separating therebetween.
The above defined simple structure comprising an inner ring formed in the inside of the first low impurity concentration semiconductor region and having an impurity concentration substantially same as the first high impurity concentration semiconductor region is effective for preventing the withstand voltage from falling when the impurity concentration of the first low impurity concentration semiconductor region is lower than the optimal level due to the functional feature of the inner ring.
While the RESURF layer operating as RESURF may be formed to have a relatively large width because of the arrangement of one or more than one inner rings in the inside of the first low impurity concentration semiconductor region, the relatively large width and the resultant relatively large surface area of the device does not give rise to any problem because the number of inner rings is minimal.